ENABLING 4K ULTRA HD CAPABILITIES THROUGH IWAVE’S ZYNQ ULTRASCALE+ MPSOC PLATFORM

The emergence of HDMI 2.0 and the widespread acceptance of this technology is making a deep impact on the multimedia and entertainment industry in our emerging economy. And the urge to support high-speed data transmission and ongoing advancements has made industries to focus on providing a diverse category of products that can support all necessary logic to deliver HDMI functionality.

The iWave’s Zynq® Ultrascale+™ MPSoC Platform supports HDMI 2.0 specifications such as bandwidth up to 18 Gbps, resolutions up to 4K @ 60 Hz, and various other key enhancements. Since it is backward compatible with the earlier version the user can integrate into existing systems with ease.

iWave’s ZU19/ZU17/ZU11 Zynq® Ultrascale+™ MPSoC development platform supports a wide range of interfaces from high speed to low speed that covers various multimedia interfaces, network interfaces, and storage devices. The combination of ARM® + Xilinx FPGA architecture presents a highly adaptive platform with high performance for multimedia applications. The System On Module(SOM) is equipped with Quad-core ARM Cortex A53 with CPU running at 1.5GHz, Dual Cortex R5 Real-Time processor running at 600MHz, ARM Mali 400MP2 Graphical Processing Unit, and up to 1143K logic elements. It has onboard 4GB DDR4 RAM with Error-correcting code for the Processing System(PS), dual 4GB DDR4 RAM for Programmable logic(PL), 8GB eMMC flash(expandable up to 128GB) for storing 4K UHD videos, and supports 12G SDI In/Out & HDMI 2.0 In/Out interfaces making it ideal for any 4K image, video or signal processing applications. Along with these it also offers SATA for extended storage via the M.2 expansion slot.

This module delivers an extensive set of peripherals such as 10G Ethernet, QSFP, FMC & FMC+ via IBERT design transceiver loopback, PMOD I/O’s, SFP+ via IBERT design from PL end and 10/100/1000Mbps Ethernet support via GEM0 & GEM3, standard SD connector via SD1, USB2.0, CAN0, I2C0, UART0 as debug, USB3.0 via PS GTR, UART, UART1, PS JTAG, PCIe as the root port, presenting diverse options to the end-user towards various used cases.

To help users to create video solutions with HDMI interfaces, the platform is incorporated with pre-packaged subsystems for HDMI transmission and reception. The HDMI 2.0 TX subsystem is hierarchically packed for easy configuration in Vivado Integrated Design Environment(IDE) interface to create required hardware accordingly. With integrated modules such as Video Timing Controller & AXI4-Stream to video out bridge, allows the HDMI 2.0 TX subsystem to support AXI4 Stream-based video input for seamless performance with other Xilinx video processing IP cores. The AXI4-Stream video interface supports dual-pixel per clock with 8 bits, 10 bits, 12bits, and 16 bits per component for RGB, YUV color spaces. The subsystem allows the end-user to build an HDMI source device that negotiates with the targeted HDMI sink device for supported features and capabilities. Communication between the source device(s) and the sink device is implemented through the Display Data Channel(DDC) lines, which is an I2C bus included on the HDMI cable. The Separate PHY and Control layer provides the user flexibility to share GTs between Receive and Transmit. And the extended display identification data(EDID) allows an engineer to easily verify the flexibility of the sink.

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Muhammad Bilal

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