X-FAB Silicon Foundries, the leading analog/mixed-signal and specialty foundry, together with crowd-sourcing IC platform partner Efabless Corporation, today announced the successful first-silicon availability of the Efabless RISC-V System on Chip (SoC) reference design. This open-source semiconductor project went from design start to tape-out in less than three months using the Efabless design flow based on open-source tools. The mixed-signal SoC, called Raven, is based on the community developed ultra-low power PicoRV32 RISC-V core. Efabless has successfully bench-tested the Raven at 100MHz, and based on simulations the design should be able to operate at up to 150MHz.
Raven is unique in that the open-source top-level design utilizes X-FAB proprietary analog IP and is created with an open-source design flow. This hybrid open-source design brings the power of open innovation and at the same time protecting significant investment in proprietary IP.
Efabless and X-FAB chose to manufacture the Raven on X-FAB’s high-reliability XH018 process. This is a flexible 180nm 6-metal process with a wide variety of options including a low power option, on-chip isolation for high voltages, and high-temperature flash memory. X-FAB’s XH018 process meets automotive quality requirementsand is popular in a wide range of automotive, industrial and medical applications.
The semiconductor design is fully functional and Efabless is now engaged with its initial customers on design of derivative offerings. To the Efabless community Raven is available from the Efabless marketplace as a reference design without license fee consequentially advancing the Efabless open innovation model of community design.
The successful partnership with Efabless demonstrates X-FAB’s continued commitment to open-source semiconductor development”, said Ulrich Bretthauer, Product Marketing Manager at X-FAB. “Nearly 75% of Raven’s die area is covered by X-FAB standard library blocks and macros. Using these proven IP blocks increased the reliability of the Raven while minimizing first-silicon risk.