NXP SEMICONDUCTORS MPC5777C POWER ARCHITECTURE® MICROCONTROLLER

NXP Semiconductors MPC5777C Power Architecture® Microcontroller is a high-performance, multicore MCU optimized for industrial and automotive control applications that require advanced performance, timing systems, security, and functional safety capabilities. The MPC5777C features two independent Power Architecture z7 cores with up to 300MHz operation, along with a single z7 core in Lockstep with one of the main cores. Integrated eTPU timers and Sigma-DeltaADC converters allow for advanced filtering using on-chip knock hardware. On-chip security encryption protection, using CSE and TDM for tamper proofing, help support ASIL-D and SIL-1 functional safety (ISO26262/ IEC61508) requirements.

NXP SEMICONDUCTORS MPC5777C POWER ARCHITECTURE® MICROCONTROLLER

The MPC5777C Power Architecture® Microcontroller is offered in a Pb-free 416-ball and 516-ball Molded Array Process Ball Grid Array (MAPBGA) package.

Features

  • Three dual-issue, 32-bit CPU core complexes (e200z7), two of which run in lockstep
    • Power Architecture embedded specification compliance
    • Instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction
    • On the two computational cores: Signal processing extension (SPE1.1) instruction support for digital signal processing (DSP)
    • Single-precision floating point operations
    • On the two computational cores: 16 KB I-Cache and 16 KB D-Cache
    • Hardware cache coherency between cores
  • 16 hardware semaphores
  • 3-channel CRC module
  • 8MB on-chip flash memory
    • Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
  • 512KB on-chip general-purpose SRAM including 64 KB standby RAM
  • Two multichannel direct memory access controllers (eDMA)
    • 64 channels per eDMA
  • Dual core Interrupt Controller (INTC)
  • Dual phase-locked loops (PLLs) with stable clock domain for peripherals and frequency modulation (FM) domain for computational shell
  • Crossbar Switch architecture for concurrent access to peripherals, flash memory, or RAM from multiple bus masters with End-To-End ECC
  • External Bus Interface (EBI) for calibration and application use
  • System Integration Unit (SIU)
  • Error Injection Module (EIM) and Error Reporting Module (ERM)
  • Four protected port output (PPO) pins
  • Boot Assist Module (BAM) supports serial bootload via CAN or SCI
  • Three second-generation Enhanced Time Processor Units (eTPUs)
    • 32 channels per eTPU
    • Total of 36KB code RAM
    • Total of 9KB parameter RAM
  • Enhanced Modular Input/Output System (eMIOS) supporting 32 unified channels
  • Two Enhanced Queued Analog-to-Digital Converter (eQADC) modules with:
    • Two separate analog converters per eQADC module
    • Support for a total of 70 analog input pins, expandable to 182 inputs with off-chip multiplexers
    • Interface to twelve hardware Decimation Filters
    • Enhanced “Tap” command to route any conversion to two separate Decimation Filters

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